Traffic Pattern Analysis for Reconfigurable Interconnects in Shared-Memory Systems

New advances in reconfigurable optical interconnect technologies will allow the fabrication of cheap, fast and run-time adaptable networks for connecting processors and memory modules in large shared-memory multiprocessor machines. Since the switching times of these components are typically high compared to the memory access time, reconfiguration can only take place on a time scale significantly above individual memory accesses. In this paper, we present preliminary results of our investigation into the exploitability of the space and time locality of address streams by a reconfigurable network. Keywords— reconfiguration, interconnection network, shared-memory, access patterns